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January 04, 2006

Verilog

I finally got a chance to start learning Verilog today. Working over break has paid off. Now if I can learn how to use the Synopsys tools, I'll be set.

Posted by ajc30 at January 4, 2006 10:59 PM

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Hi,
I'm a new PhD student at Case (EECS). I just want to know if Synopsys Design is available here?
I've used Synopsys before and probably I'll need it for my future work...

Posted by: Masoud at January 20, 2006 04:57 PM

There is Synopsys on the computers in the VLSI lab on the 8th floor of Olin.

Posted by: Alex at March 1, 2006 12:29 PM

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